1. Field of the Invention
The present invention relates to a threshold analysis system and a threshold analysis method, and more particularly, it relates to a threshold analysis system and a threshold analysis method capable of deciding threshold voltages of all cells included in a memory device through single processing.
2. Description of the Background Art
In design evaluation of a flash memory, threshold voltage distribution of transistors must be obtained by applying temperature stress or the like, in order to guarantee the quality of the product. In particular, it is important to efficiently calculate threshold voltages to catch up with the recent increase of the capacity of the flash memory.
The threshold voltage is the minimum voltage for feeding a current to each transistor. In general, the threshold voltage can be detected by changing the voltage level of a word line connected to the gate of the transistor at regular intervals and confirming whether or not the transistor is rendered conductive.
Japanese Patent Laying-Open No. 4-195899 (1992) discloses a method of automatically generating a voltage applied to the gate of a transistor while employing binary search for efficiently detecting the threshold voltage.
In the method disclosed in Japanese Patent Laying-Open No. 4-195899, however, the threshold voltage is obtained bit by bit. In this method, therefore, it takes much time to obtain threshold voltages of a bulk flash memory, leading to inferior efficiency.
Even if a result of processing is obtained, it is difficult for a user to grasp a tendency such as dispersion of the process.
Accordingly, an object of the present invention is to provide a threshold analysis system and a threshold analysis method capable of efficiently calculating threshold voltages of a memory device such as a flash memory.
Another object of the present invention is to provide a threshold analysis system capable of expressing the tendency of threshold voltages that is readily grasped.
A threshold analysis system according to an aspect of the present invention includes a signal generation circuit generating a plurality of types of voltages and sequentially applying each of the plurality of types of voltages to a plurality of cells forming a memory device, an address generator sequentially generating address signals specifying the respective ones of the plurality of cells, a memory storing data read from the memory device as fail bit map information as to each of the plurality of types of voltages, and a threshold voltage calculation part connected to the memory for calculating threshold voltages of the plurality of cells forming the memory device from a plurality of pieces of fail bit map information corresponding to the plurality of types of voltages.
The threshold analysis system calculates the threshold voltages of the plurality of cells on the basis of the plurality of pieces of fail bit map information. Therefore, the threshold analysis system can simultaneously calculate the threshold voltages of the respective cells in the memory device, for efficiently calculating the threshold voltages.
Preferably, the signal generation circuit and the address generator are formed by a signal generation circuit and a pattern generator included in a memory tester respectively, while the memory and the threshold voltage calculation part are formed by a fail memory and a central processing unit included in a repair analysis device respectively.
The threshold analysis system is formed by the memory tester and the repair analysis device. Therefore, threshold analysis can be made through general purpose devices, with no requirement for specific hardware.
More preferably, each of the plurality of pieces of fail bit map information has a prescribed size, and is stored in a continuous area of the fail memory.
The size of the fail bit map information is preset and the fail bit map information is continuously stored. Assuming that the size of the fail bit map information is expressed as OffsetAdrs and the head address of the first fail bit map information is 0, therefore, the head address of i-th fail bit map information can be expressed as (ixe2x88x921)xc3x97OffsetAdrs. Thus, each fail bit map information can be readily accessed.
More preferably, the memory has a two-bank memory structure for alternating banks every time a voltage applied to the memory device is changed and writing fail bit map information in one of the banks with reference to fail bit map information stored in another bank.
The memory writes the fail bit map information in one of the banks with reference to the fail bit map information stored in another bank. Data may not be reread in relation to a cell failing in data reading. Therefore, the fail bit map information can be created at a high speed.
More preferably, the signal generation circuit is formed by a signal generation circuit included in a memory tester, and the address generator and the threshold voltage calculation part are formed by a digital signal processor.
The threshold analysis system is formed by the memory tester and the digital signal processor. Therefore, threshold analysis can be made through general purpose devices, with no requirement for specific hardware.
More preferably, the threshold analysis system further includes a threshold display part connected to the threshold voltage calculation part for visually displaying the threshold voltages of the plurality of cells.
The threshold analysis system can visually express the threshold voltages. Therefore, a user can readily grasp a tendency such as dispersion of the process.
More preferably, the threshold display part includes a difference value calculation part for calculating a difference value between threshold voltages obtained under two states having different conditions and a difference value display part connected to the difference value calculation part for visually displaying the difference value.
A cell exhibiting a large difference value can be determined as faulty by visually expressing the difference value between the threshold voltages.
A threshold analysis method according to another aspect of the present invention is employed in a threshold analysis system including a signal generation circuit generating a plurality of types of voltages and sequentially applying each of the plurality of types of voltages to a plurality of cells forming a memory device, an address generator sequentially generating address signals specifying the respective ones of the plurality of cells, a memory storing data read from the memory device as fail bit map information as to each of the plurality of types of voltages and a threshold voltage calculation part connected to the memory for calculating threshold voltages of the plurality of cells forming the memory device from a plurality of pieces of fail bit map information corresponding to the plurality of types of voltages. The threshold analysis method includes steps of sequentially applying each of the plurality of types of voltages to the plurality of cells, sequentially generating the address signals specifying the respective ones of the plurality of cells, storing data read from the memory device as fail bit map information as to each of the plurality of types of voltages and calculating threshold voltages of the plurality of cells forming the memory device from the plurality of pieces of fail bit map information stored in the memory.
The threshold voltages of the plurality of cells are calculated on the basis of the plurality of pieces of fail bit map information. Therefore, the threshold voltages of the respective cells in the memory device can be simultaneously calculated, for efficiently calculating the threshold voltages.